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期刊


ISSN1350-2409
刊名IEE proceedings
参考译名英国电气工程师学会论文集：电子线路与系统
收藏年代1998～2006

关联期刊参考译名收藏年代
IET Circuits, Devices & SystemsIET电子线路与系统2007～2012


全部

1998 1999 2000 2001 2002 2003
2004 2005 2006

2005, vol.152, no.1 2005, vol.152, no.2 2005, vol.152, no.3 2005, vol.152, no.4 2005, vol.152, no.5 2005, vol.152, no.6

题名作者出版年年卷期
Computational paradigm for nanoelectronics: self-assembled quantum dot cellular neural networksS. Bandyopadhyay; K. Karahaliloglu; S. Balkir; S. Pramanik20052005, vol.152, no.2
Linearisation of a common emitter RF amplifier using augmentationN. Tilston; A. D. McLachlan; A. J. Sangster20052005, vol.152, no.2
Fourth-order PLL loop filter design technique with invariant natural frequency and phase marginI. V. Thompson; P. V. Brennan20052005, vol.152, no.2
Lossless vector-quantised index coding design and implementationP.-Y. Chen; C.-T. Yu20052005, vol.152, no.2
Low-power single- and double-edge-triggered flip flops for high-speed applicationsS. H. Rasouli; A. Khademzadeh; A. Afzali-Kusha; M. Nourani20052005, vol.152, no.2
0.7V Manchester carry look-ahead circuit using PD SOI CMOS asymmetrical dynamic threshold pass transistor techniques suitable for low-voltage CMOS VLSI systemsT. Y. Chiang; J. B. Kuo20052005, vol.152, no.2
Low power high-speed CMOS dual-modulus prescaler design with imbalanced phase-switching techniqueX. P. Yu; M. A. Do; J. G. Ma; K. S. Yeo; R. Wu; G. Q. Yan20052005, vol.152, no.2
Efficient method to obtain the entire active area against circuit delay time trade-off curve in gate sizingJ. A. Montiel-Nelson; J. Sosa; H. Navarro; R. Sarmiento; A. Nunez20052005, vol.152, no.2
Output buffer design for low noise and load adaptabilityL. Yang; J. S. Yuan20052005, vol.152, no.2
Design of an area-efficient CMOS multiple-valued current comparator circuitZ.-H. Kong; K.-S. Yeo; C.-H. Chang20052005, vol.152, no.2
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