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2019, vol.48, no.1	2019, vol.48, no.2	2019, vol.48, no.3	2019, vol.48, no.4	2019, vol.48, no.5	2019, vol.48, no.6
2019, vol.48, no.7	2019, vol.48, no.8

题名	作者	出版年	年卷期
Multilevel Bipolar Memristor Model Considering Deviations of Switching Parameters in the Verilog-A Language	G. S. Teplov; E. S. Gornev	2019	2019, vol.48, no.3
Logical C-Element on STG DICE Trigger for Asynchronous Digital Devices Resistant to Single Nuclear Particles	Yu. V. Katunin; V. Ya. Stenin	2019	2019, vol.48, no.3
Monte Carlo Simulation of Defects of a Trench Profile in the Process of Deep Reactive Ion Etching of Silicon	M. K. Rudenko; A. V. Myakon'kikh; V. F. Lukichev	2019	2019, vol.48, no.3
Methods and Algorithms for the Logical-Topological Design of Microelectronic Circuits at the Valve and Inter-Valve Levels for Promising Technologies with a Vertical Transistor Gate	G. A. Ivanova; D. I. Ryzhova; S. V. Gavrilov; N. O. Vasilyev; A. L. Stempkovskii	2019	2019, vol.48, no.3
Layout Synthesis Design Flow for Special-Purpose Reconfigurable Systems-on-a-Chip	S. V. Gavrilov; D. A. Zheleznikov; M. A. Zapletina; V. M. Khvato; R. Zh. Chochaev; V. I. Enns	2019	2019, vol.48, no.3
Extracting a Logic Gate Network from a Transistor-Level CMOS Circuit	D. I. Cheremisino; L. D. Cheremisinova	2019	2019, vol.48, no.3
Reflection Spectra Modification of Diazoquinone-Novolak Photoresist Implanted with B and P Ions	D. I. Brinkevich; A. A. Kharchenko; V. S. Prosolovich; V. B. Odzhaev; S. D. Brinkevich; Yu. N. Yankovskii; Yu. Kornienko	2019	2019, vol.48, no.3