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期刊


ISSN0913-5685
刊名電子情報通信学会技術研究報告
参考译名电子信息通信学会技术研究报告：电子装置
收藏年代2000～2022

关联期刊参考译名收藏年代
電子情報通信学会技術研究報告电子信息通信学会技术研究报告：电子装置 


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2000 2001 2002 2003 2004 2005
2006 2007 2008 2009 2010 2011
2012 2013 2014 2015 2016 2017
2018 2019 2020 2021 2022

2000, vol.100, no.1 2000, vol.100, no.147 2000, vol.100, no.148 2000, vol.100, no.149 2000, vol.100, no.2 2000, vol.100, no.235
2000, vol.100, no.236 2000, vol.100, no.265 2000, vol.100, no.266 2000, vol.100, no.305 2000, vol.100, no.306 2000, vol.100, no.318
2000, vol.100, no.370 2000, vol.100, no.405 2000, vol.100, no.406 2000, vol.100, no.505 2000, vol.100, no.506 2000, vol.100, no.547
2000, vol.100, no.548 2000, vol.100, no.549 2000, vol.100, no.57 2000, vol.100, no.58 2000, vol.100, no.641 2000, vol.100, no.642
2000, vol.100, no.683

题名作者出版年年卷期
A 60ns Access 32kByte three-transistor flash (TTF) for low power embedded applicationsTakuya Futatsuyama; Kenichi Imamiya; Junichiro Noda; Tamio Ikehashi; Masaki Ichikawa; Akira Iwata20002000, vol.100, no.265
Dynamically reconfigurable logic LSI - PCA-1Hideyuki Ito; Ryusuke Konishi; Hiroshi Nakada; Kiyoshi Oguri; Kouichi Nagami; Tsunemichi Shiozawa; Norbert Imlig; Minoru Inamori; Akira Nagoya20002000, vol.100, no.265
Skew and jitter suppressed DLL architecture for over 400 Mbps DDR SDRAMsTakeshi Hamamoto; Satoshi Kawasaki; Kiyohiro Furutani; Kenichi Yasuda; Yasuhiro Konishi20002000, vol.100, no.265
Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIsYusuke Kanno; Hiroyuki Mizuno; Kazuo Tanaka; Takao Watanabe20002000, vol.100, no.265
On-chip multi-GHz clocking with transmission linesK. Anjo; M. Mizuno; Y. Sumi; M. Fukaishi; H. Wakabayashi; T. Mogami; T. Horiuchi; M. Yamashina20002000, vol.100, no.265
900MHz 18Mb DDR SRAMYasuhisa Takeyama; Atsushi Kawasumi; Azuma Suzuki; Hiroshi Hatada; Osamu Hirabayashi; Yasushi Kameda; Takahiro Hamano; Nobuaki Otsuka20002000, vol.100, no.265
A 54×54-b multiplier with a triple-Vth CMOS/SIMOX circuit schemeKoji Fujii; Takakuni Douseki20002000, vol.100, no.265
A 450MHz 64bit RISC processor using multiple threshold voltage CMOSTakeo Yamashita; Naoki Yoshida; Masatoshi Sakamoto; Takashi Matsumoto; Mitsugu Kusunoki; Hideyuki Takahashi; Atsushi Wakahara; Takuji Ito; Teruhisa Shimizu; Kozaburo Kurita; Keiichi Higeta; Kazutaka Mori; Nobuo Tamba; Naoki Kato; Kazuhisa Miyamoto20002000, vol.100, no.265
2-step fast modified-breaking-off-search motion estimation algorithm for MPEG4 and low-power CMOS motion estimation LSIAkira Kotabe; Tadayoshi Enomoto20002000, vol.100, no.265
Communication services in post IMT-2000 ageHiroshi Yasuda20002000, vol.100, no.265
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